BBD delay line compander

[itoa]

Thanks for deep explanations ! I will need some time to get through your explanations.
I want to understand the single transition.. and "sucking dry" the discharging cap . Gonna meditate on your text.. I've heard some doubtfull opinions on "box filtering" like actions and leakage to side caps, I want to see this

In the meanwhile found a transition equation here:
http://anothersample.net/order/4cf0bf70 ... d8647d0ff0?

Take a look at Fig.1 and corresponding formula. But I don't get it.. Vt is treshold voltage? Why the output approaches VG - VT then... Isn't this value constant?

[JCJR]

Hi Itoa. My explanation isn't deep and may be horribly wrong. Just winging it. Will read that paper you found.

1. For instance if we start with cap #1 and cap #2 each at 6 volts. When 12 volts is applied to the back end of cap #2 and a resistive path is opened thru the switching FET to cap #1. Cap #2 is initially 6 + 12 = 18 volts, and cap #1 at 6 volts. The 12 volt differential causes charge to transfer between the two caps. The charge transfer is slowed by the on-resistance of the switching FET. The voltage on cap #1 would rise while the voltage on cap #2 falls, as the charge tries to equalize. So after the clock 2 toggles to ground and subtracts 12 volts from cap #2, it seems that cap #2 ought to end up at somewhere less than the 6 volts which it started out with, before that clock cycle happened?

2. If cap #1 is at 7 volts and cap #2 at 6 volts, then when cap #2 gets clocked there is only 11 volts differential between the caps, so cap #2 would not fall in voltage as much as in case #1. Therefore when clock 2 goes to ground and subtracts 12 volts, then cap #2 would have a higher ending value than in case #1 above?

3. If cap #1 is at 5 volts and cap #2 is at 6 volts, then when cap #2 gets clocked there is 13 volts differential between the caps, so cap #2 would fall lower in voltage than in case #1.

So that seems to explain how signal gets pulled from one cap to the next. I'm just puzzled why the circuit doesn't act kinda like a demented charge pump, driving the DC level lower and lower on each clock cycle.

[itoa]

Aciddose are you there?

[JCJR]

OK, Doh, think I know why the caps DC level doesn't get pumped down lower and lower on each clock cycle--

The DC level of cap #2 falls after it has sampled cap #1, but then the DC level of cap #2 gets pulled back up when it gets sampled by cap #3, and so forth all the way down the line.

Another factor may be leakage of these tiny capacitors helping keep things centered. Dunno how modern DRAM works, but some older DRAM would remember the value of bits with tiny capacitors, each cap buffered by gates so it can hold a charge at all. Those DRAMs had to be refreshed constantly and frequently or the caps would leak off and lose their memory.

So maybe the tiny caps in a BBD are constantly leaking and do not have long enough memory to accumulate serious DC offsets from the charge pumping?

The volatility of the caps, a factor in addition to the "pull up" effect when the cap gets sampled by the next S&H down the line.

[JCJR]

OK, from puzzling over the paper a bit--

One FET threshold parm is the "pinch off" threshold. For an n-channel device, some gate voltage below the voltage of the source terminal, where the FET gets very high resistance measured in megohms. So if you wanted to design an N channel FET switch for a stomp box, if your signal's DC level going thru the source and drain terminals is around 0 volts, then if you want to turn off the switch you would apply a negative voltage to the gate, at or below the pinch off thresh. If you apply a voltage of 0 volts or bigger than 0 volts, at some positive gate voltage the resistance of the FET will get as low as its gonna get. Between the pinch-off threshold and a large positive gate voltage, the resistance of the FET keeps getting lower.

If you want to make a class a amplifier, you could connect a resistor to V+ and connect the other end of the resistor to the drain of the N channel FET, and connect the source terminal of the FET to ground. Then adjust the input bias on the gate terminal to some negative voltage which is just low enough to make the FET have the same resistance as that resistor connected to V+. That makes a resistor divider and half of V+ volts at the output junction between the FET drain and the resistor. Now if you inject audio into the gate terminal, making the bias voltage wiggle up and down, the resistance of the FET would wiggle up and down more drastically, making the output of the voltage divider wiggle up and down, giving you audio gain. In a practical circuit you would use resistors and capacitors to set up the bias voltage, and use feedback resistors to help minimize distortion in the amplifier.

****

So anyway, I think it is another kind of threshold mentioned in that BBD noise paper-- Am guessing that they are referring to a threshold where if the voltage difference between drain and source gets real small, the FET behaves differently (and might become more noisy, dunno).

They say the threshold problem gets worse with low clocking frequencies, and the charging curve they show-- My guess is that with a low clock frequency, each S&H stays gated open long enough to allow the voltage between the two capacitors to almost completely equalize. When that happens, the voltage on both capacitors would be nearly the same. Obviously the voltage across the source and drain terminals of that switch FET in-between the two capacitors would also get very small. I think that is the threshold they are talking about but could be mistaken.

Around the last page figure 6 they show that a clock rate of 100 kHz is much less noisy than a clock rate of 10 kHz, and the noise spectrum looks different.

They blame most of the noise below 2 kHz on 1/f noise and blame the higher frequency noise on johnson/nyquist.

1/f noise usually has a pink spectrum, -3 dB per octave. Johnson/nyquist noise usually has a white spectrum for audio purposes, but is supposedly gaussian when considering a very wide frequency range.

So maybe the crudest modeling would just add more noise at lower clock rates, and especially add more pink than white noise at lower clock rates? If the LFO is modulating the clock rate over a fairly wide range, then I suppose the noise would modulate up and down along with the LFO at least a little bit?

[very angry mobster]

I would love to have a sample of square wave passed through bbd in the loop.

https://app.box.com/s/copvzg3sa9fe851nia2gvzvkdxte2le0

This is a ~40hz square, followed by a ~40hz sine run through a Pittsburgh Analog Delay.

Recorded using an Expert Sleepers ES6 module.

The Analog Delay rolls off the top end noticeably. The signal degradation is quite obvious with long delay times as well.

Shout if there's any other test signals you'd like run through the module.


Shannon

[itoa]

Thanks a lot!
Wow this thing is dirty.

AA filter at 2khz.
Asymmetrical shaping/filtering - different slopes
Its like.. hmm frequency modulated, or there is a strong clock jitter, no idea.

[very angry mobster]

Yep, it's quite dirty, especially at the long delay settings. In the right contexts, the dirt adds to the sound in a very likable way IMHO.

[JCJR]

Yeah BBD can get nasty.

Itoa, I keep saying Captain Obvious things, can't help it. Sorry bout that. There is asymmetry. And there is anti-alias lowpass filtering.

The other detail, you probably know this-- The MOST LIKELY cause of that fairly straight-line downward tilt on the "middle sections" of the square wave tops-- It is probably not distortion, and possibly unrelated to the BBD chip at all. The downward sloping square wave tops are probably just linear hipass filtering because of "too small" dc coupling capacitors on the input and/or output of the circuit.

Possibly there could be something in the nature of a BBD which causes "built-in" high passing. However, such a proposition is not necessary to explain the square wave sloping tops. Tis quite possible that this effect could be minimized simply by using bigger coupling capacitors. On the other hand, the BBD may sound better in context of some sounds, hipassing very low pitches, better emphasizing higher frequencies.

Just wanted to help, in case you didn't already know the likely cause of the sloping square wave tops. Avoid wasting time trying to figure them out. You can get the sloping square wave tops just by adding first order hipass filters on the input and/or output.

[very angry mobster]

Removing DC offsets with a hipass filter would give you a little more headroom and likely be beneficial when using high feedback amounts as well.

[JCJR]

Yes, wasn't criticizing that bbd unit for having "too much" hipassing. Was just mentioning a possible reason for the tilted square wave tops, if that might not have been already known. I wouldn't be surprised if many such devices would intentionally tune the hipass filters rather high.

[itoa]

Digging deeper in the background

btw. here are some nice examples
http://www.strymon.net/brigadier/
I know its DSP but they emulations are deep.
Listen to "bucket loss" demo, a lot of things are happening there. (you can see even PSU hum in spectrum)

Just read some papers about noise in CCD's. Another interesting phenomenon: different kind of noise is generated for loading and unloading

I'm sure that static distortion and adding noise will not model internal loss properly.