One FDIV per clock cycle, but a 6 cycle latency.aciddose wrote:it is better to use a divide or multiply than a bitshift in most cases on modern cpus, and always in c/c++ langauge. the divide or multiply will get optimized to the best form by the compiler, while if you use a bitshift it will not.
in any case, a bitshift will take the same number of cycles as a divide or multiply.. either as a single opcode or in a lea, they all take one cycle. the use of bitshifts in place of multiplies/divides is an artifact of older architectures and is really no longer nessicary in almost all cases.
many multiples/divides will get optimized selectively to both bitshifts and leas on the x86 because sometimes it is more advantageous to use one than the other.
If the divs are SSE2, it means you can do four single precision divs per clock cycle, but on the other hand, BarenB's bit ops are probably going to pipeline nicely, using only the integer ALU. I think the FPU should be a lot faster if you can keep it fed, not a problem considering the type of data and the nature of the problem.
I realize I'm out of my depth here. My assembly experience includes MIPS and early X86, and I'm only a wannabe DSP programmer. But this topic does really interest me.
Thanks!
