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Modular Synth design and releases (Reaktor, SynthEdit, Tassman, etc.)
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vortico wrote:Image It's right there on the toolbar.

No VST parameters, for the first version of VCV Bridge at least.
Sorry, if I was not clear. I know that I can run the VCVrack at higher rate.
What I meant is that it would be useful in the future VST bridge if it was possible to run Rack at a higher rate than the output buffer expects.

On the other hand, one can always run the whole DAW at higher rate (if the CPU allows...)

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Project and plugins build, I reinstall msys2, follow the vcv notes, copy lib and .h files of samplerate library into the lib and include folders into dep (because make rack gives me "cannot find samplerate.h"), and it finnally works. thanks a lot, I can began the funny parts...

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martin_l wrote:
Sorry, if I was not clear. I know that I can run the VCVrack at higher rate.
What I meant is that it would be useful in the future VST bridge if it was possible to run Rack at a higher rate than the output buffer expects.

On the other hand, one can always run the whole DAW at higher rate (if the CPU allows...)
Yes, that's what that toolbar button does. The device sample rate is set on the Audio Interface, and both that and Bridge will convert to/from the device/DAW sample rate if different.
Last edited by vortico on Thu Sep 21, 2017 12:14 am, edited 1 time in total.
VCV Rack, the Eurorack simulator

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rafzael wrote:Project and plugins build, I reinstall msys2, follow the vcv notes, copy lib and .h files of samplerate library into the lib and include folders into dep (because make rack gives me "cannot find samplerate.h"), and it finnally works. thanks a lot, I can began the funny parts...
That likely means libsamplerate wasn't built correctly. I'd suggest deleting the samplerate directory and rerunning `make`. If the headers don't get copied, it's probably not building the library, so you should solve that problem first.
VCV Rack, the Eurorack simulator

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vortico wrote:
martin_l wrote:
Sorry, if I was not clear. I know that I can run the VCVrack at higher rate.
What I meant is that it would be useful in the future VST bridge if it was possible to run Rack at a higher rate than the output buffer expects.

On the other hand, one can always run the whole DAW at higher rate (if the CPU allows...)
Yes, that's what that toolbar button does. The device sample rate is set on the Audio Interface, and both that and Bridge will convert to/from the device/DAW sample rate if different.
Ah, very good! Sorry, that was not clear to me. I guess many great features of the software will only come up slowly and when at some point a manual emerges.

It's really a great synth! Also the API, even if not yet finialized, looks very good to me. Easy to understand and handle. It only took me a few hours from getting the code to having some working prototypes of new modules ready.

Thanks a lot for all your effort!

Cheers,
Martin

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some quite extreme waveshaping using some custom modules I am working on

https://www.youtube.com/watch?v=x5FC0Sl ... e=youtu.be

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That's very cool!

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Thank you vortico, I just put header and lib files into the directories (lib and include in dep) and it seems to be working. I just finished a little dual frequency divider (one can divide by 2, 4, 8 and the other by 2, 3 and 4) with reset button and reset input. Could be useful to get sequencers running at diffrent relative speed, create sub oscillator (but the output is actually oscillating from 0 to 10 and not from -10 to 10), count gate or trig events,... By combining the dividers it s possible to divide by 2, 3, 4, 6, 8, 12, 16, 24, 32

Image

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I was looking to create a frequency divider (to divide clock signals) but couldn't manage to.
A sneak peek into the code? ;-)

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I managed to build my Module Pack for both MAC and PC.
I am releasing a preliminary BETA with only 3 modules.

It SHOULD work on Rack 0.31.
Please test it and let me know ;-)

You can find the download and installation instructions here on my website:

http://www.autodafe.net/blog/10-vcv-rac ... a-0-8.html

Any feedback appreciated, here or in the comments on my website

Image

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work OK for me on 64bit Win10
very nice

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thx a lot. will try to release more in a few days :-)

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Hello, of course here is the code I wrote, I add this in the befaco plugins (I will create my own plugins series latter). All work prefectly except the reset function : the count index of the divider stay to zero when you push the button or send an active gate to a reset input, I will modify it soon for a reset only on the rising edge of the gate (or push moment of the button).
In any case, develop modules for this software is realy plaisant, VCV have done a great great job. Maybe it coud be nice to gather our plugins series on a same website or FB page or...Some insterested?

I also change the panel :)

Image

#include "Befaco.hpp"
struct FrequencyDivider : Module {
enum ParamIds {
DIVIDER1_PARAM,
DIVIDER2_PARAM,
RESET1_PARAM,
RESET2_PARAM,
NUM_PARAMS
};
enum InputIds {
CLOCK1_INPUT,
CLOCK2_INPUT,
RESET1_INPUT,
RESET2_INPUT,
NUM_INPUTS
};
enum OutputIds {
DIVIDED_CLOCK1_OUTPUT,
DIVIDED_CLOCK2_OUTPUT,
NUM_OUTPUTS
};
int clock1Count = 0;
int clock2Count = 0;
//float lights[4] = {};
SchmittTrigger trigger1;
SchmittTrigger trigger2;
SchmittTrigger reset1;
SchmittTrigger reset2;
FrequencyDivider();
void step();
};


FrequencyDivider::FrequencyDivider() {
params.resize(NUM_PARAMS);
inputs.resize(NUM_INPUTS);
outputs.resize(NUM_OUTPUTS);
trigger1.setThresholds(0.0, 1.0);
trigger2.setThresholds(0.0, 1.0);
reset1.setThresholds(0.0, 1.0);
reset2.setThresholds(0.0, 1.0);
}

void FrequencyDivider::step() {
//bool clock1HIGH = getf(inputs[CLOCK1_INPUT]) >= 1.0;
//bool clock2HIGH = getf(inputs[CLOCK2_INPUT]) >= 1.0;
int divider1;
switch ((int)roundf(params[DIVIDER1_PARAM])) {
case 0: divider1 = 2; break;
case 1: divider1 = 4; break;
default: divider1 = 8; break;
}
int divider2;
switch ((int)roundf(params[DIVIDER2_PARAM])) {
case 0: divider2 = 2; break;
case 1: divider2 = 3; break;
default: divider2 = 4; break;
}
//ll
bool reset = false;

if (reset1.process(params[RESET1_PARAM]))
{
clock1Count = 0;
reset = true;
}
if (reset2.process(params[RESET2_PARAM]))
{
clock2Count = 0;
reset = true;
}
if ((clock1Count >= divider1) || (reset1.process(getf(inputs[RESET1_INPUT]))))
{
clock1Count = 0;
reset = true;
}
if ((clock2Count >= divider2) || (reset1.process(getf(inputs[RESET2_INPUT]))))
{
clock2Count = 0;
reset = true;
}

if (clock1Count < divider1/2)
{
setf(outputs[DIVIDED_CLOCK1_OUTPUT], 10.0);
}
else
{
setf(outputs[DIVIDED_CLOCK1_OUTPUT], 0.0);
}

if (clock2Count < divider2/2)

{
setf(outputs[DIVIDED_CLOCK2_OUTPUT], 10.0);
}
else
{
setf(outputs[DIVIDED_CLOCK2_OUTPUT], 0.0);
}
if ( reset == false)
{
if (trigger1.process(getf(inputs[CLOCK1_INPUT])) && clock1Count <= divider1 )
{
clock1Count++;
}
if (trigger2.process(getf(inputs[CLOCK2_INPUT])) && clock2Count <= divider2 )
{
clock2Count++;
}
}


//lights[0] = out / 5.0;
}


FrequencyDividerWidget::FrequencyDividerWidget() {
FrequencyDivider *module = new FrequencyDivider();
setModule(module);
box.size = Vec(15*5, 380);

{
SVGPanel *panel = new SVGPanel();
panel->box.size = box.size;
panel->setBackground(SVG::load("plugins/Befaco/res/FrequencyDivider.svg"));
addChild(panel);
}

addChild(createScrew<ScrewBlack>(Vec(15, 0)));
addChild(createScrew<ScrewBlack>(Vec(15, 365)));

addParam(createParam<NKK>(Vec(19, 100), module, FrequencyDivider::DIVIDER1_PARAM, 0.0, 2.0, 2.0));
addParam(createParam<NKK>(Vec(19, 100+180), module, FrequencyDivider::DIVIDER2_PARAM, 0.0, 2.0, 2.0));

addParam(createParam<LEDButton>(Vec(4, 150), module, FrequencyDivider::RESET1_PARAM, 0.0, 1.0, 0.0));
addParam(createParam<LEDButton>(Vec(4, 150+180), module, FrequencyDivider::RESET2_PARAM, 0.0, 1.0, 0.0));

addInput(createInput<PJ3410Port>(Vec(35, 150), module,FrequencyDivider::RESET1_INPUT));
addInput(createInput<PJ3410Port>(Vec(35, 150+180), module, FrequencyDivider::RESET2_INPUT));

addInput(createInput<PJ3410Port>(Vec(19, 27), module,FrequencyDivider::CLOCK1_INPUT));
addInput(createInput<PJ3410Port>(Vec(19, 27+180), module, FrequencyDivider::CLOCK2_INPUT));

addOutput(createOutput<PJ3410Port>(Vec(19, 68), module, FrequencyDivider::DIVIDED_CLOCK1_OUTPUT));
addOutput(createOutput<PJ3410Port>(Vec(19, 68+180), module, FrequencyDivider::DIVIDED_CLOCK2_OUTPUT));

}

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[never mind]
VCV Rack, the Eurorack simulator

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thanks a lot.
i hacked your code to create a Clock Divider, more or less cloned from Doepfer A-160:

https://www.youtube.com/watch?v=nmiL9Tr8ar4

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